10AX115H2F34E2SG FPGA Arria® 10 ʻOhana GX 1150000 Kelepona 20nm ʻenehana 0.9V 1152-Pin FC-FBGA
Nā Kūlana Kūlana Huahana
| EU RoHS | Hoʻokō |
| ECCN (US) | 3A991 |
| Kūlana Māhele | ʻeleu |
| HTS | 8542.39.00.01 |
| SVHC | ʻAe |
| ʻOi aku ka SVHC i ka paepae | ʻAe |
| Kaʻa kaʻa | No |
| PPAP | No |
| Inoa ʻohana | Arria® 10 GX |
| ʻenehana hana | 20nm |
| Mea hoʻohana I/Os | 504 |
| Ka helu o na kakau inoa | 1708800 |
| Ka Voltage Hoʻolako Hana (V) | 0.9 |
| ʻElemu Loko | 1150000 |
| Ka helu o na mea hoonui | 3036 (18x19) |
| ʻAno hoʻomanaʻo papahana | SRAM |
| Hoʻomanaʻo i hoʻokomo ʻia (Kbit) | 54260 |
| Huina huina o ka poloka RAM | 2713 |
| Nā EMAC | 3 |
| Nā Unite Logic Device | 1150000 |
| Helu lako o nā DLL/PLL | 32 |
| Nā Kanika Transceiver | 96 |
| Ka wikiwiki o ka lawe ʻana (Gbps) | 17.4 |
| DSP hoʻolaʻa | 1518 |
| PCIe | 4 |
| Hiki i ka polokalamu | ʻAe |
| Kākoʻo Reprogrammability | ʻAe |
| Palekana kope | ʻAe |
| Hiki i loko o ka Pūnaewele | ʻAe |
| Papa māmā | 2 |
| Nā Kūlana I/O Hoʻokahi-Hoʻopau | LVTTL|LVCMOS |
| Pānaʻi hoʻomanaʻo waho | DDR3 SDRAM|DDR4|LPDDR3|RLDRAM II|RLDRAM III|QDRII+SRAM |
| ʻO ka ʻuala hoʻolako hana liʻiliʻi loa (V) | 0.87 |
| ʻO ka Voltage Hoʻohana Nui (V) | 0.93 |
| Voltage I/O (V) | 1.2|1.25|1.35|1.5|1.8|2.5|3 |
| Mahana hana liʻiliʻi loa (°C) | 0 |
| ʻO ka wela hoʻohana kiʻekiʻe loa (°C) | 100 |
| Papa Mahana Mea Hoʻolako | Hoʻonui ʻia |
| inoa kalepa | ʻO Arria |
| Ke kau ʻana | Mauna ʻili |
| Kiʻekiʻe pūʻolo | 2.95 |
| Laulā Pūʻolo | 35 |
| Ka lōʻihi o ka pūʻolo | 35 |
| Ua loli ka PCB | 1152 |
| Inoa Pūʻolo maʻamau | BGA |
| Pūʻolo Mea Hoʻolako | FC-FBGA |
| Helu Pin | 1152 |
| ʻAno alakaʻi | kinipopo |
ʻO ka ʻokoʻa a me ka pilina ma waena o FPGA a me CPLD
1. FPGA wehewehe a me nā hiʻohiʻona
FPGAhoʻohana i kahi manaʻo hou i kapa ʻia ʻo Logic Cell Array (LCA) a me Configurable Logic Block (CLB) a me Input Output (IOB) Block and Interconnect.ʻO ka module logic configurable ka ʻāpana kumu e ʻike ai i ka hana o ka mea hoʻohana, i hoʻonohonoho pinepine ʻia i loko o kahi ʻāpana a hoʻolaha i ka chip holoʻokoʻa.Hoʻopiha ka module input-output IOB i ka pilina ma waena o ka loiloi ma ka chip a me ka pine o waho, a ua hoʻonohonoho pinepine ʻia a puni ka ʻāpana chip.Aia ka uwea kūloko i nā lōʻihi like ʻole o nā ʻāpana uea a me kekahi mau hoʻololi pili programmable, kahi e hoʻopili ai i nā poloka logic programmable a i ʻole nā poloka I/O e hana i kahi kaapuni me kahi hana kikoʻī.
ʻO nā hiʻohiʻona kumu o FPGA:
- Ke hoʻohana nei i ka FPGA e hoʻolālā i ka kaapuni ASIC, ʻaʻole pono nā mea hoʻohana i ka hana papahana, hiki ke loaʻa i kahi chip kūpono;
- Hiki ke hoʻohana ʻia ka FPGA ma ke ʻano he hoʻohālike hoʻokele o nā mea ʻē aʻe i hana ʻia a i ʻole semi-customizedASIC kaapuni;
- Nui nā mea hoʻoulu a me nā pine I/O ma FPGA;
- ʻO FPGA kekahi o nā mea hana me ka pōkole hoʻolālā pōkole loa, ke kumu kūʻai haʻahaʻa haʻahaʻa a me ka haʻahaʻa haʻahaʻa loa i ka kaapuni ASIC.
- Hoʻohana ʻo FPGA i ke kaʻina CHMOS kiʻekiʻe, ka hoʻohana haʻahaʻa haʻahaʻa, a hiki ke kūpono me nā pae CMOS a me TTL.
2, wehewehe CPLD a me nā hiʻohiʻona
CPLDka mea nui i haku ʻia me ka programmable Logic Macro Cell (LMC) a puni ke kikowaena o ka programmable interconnection matrix unit, kahi o ka LMC logic structure i ʻoi aku ka paʻakikī, a he paʻakikī I / O unit interconnection structure, hiki ke hana ʻia e ka mea hoʻohana e like me nā pono o ka hoʻolālā kaapuni kūikawā, e hoʻopau i kekahi mau hana.Ma muli o ka pili ʻana o nā poloka logic me nā uea metala lōʻihi paʻa i ka CPLD, ʻo ke kaʻapuni logic i hoʻolālā ʻia he hiki ke wānana i ka manawa a pale i ka hemahema o ka wanana piha ʻole o ka manawa o ka hoʻolālā interconnect segmented.Ma ka 1990s, ua ulu wikiwiki ka CPLD, ʻaʻole wale me nā hiʻohiʻona holoi uila, akā me nā hiʻohiʻona holomua e like me ka nānā ʻana a me ka hoʻonohonoho pūnaewele.
ʻO nā hiʻohiʻona o ka polokalamu CPLD penei:
- He nui nā kumuwaiwai noʻonoʻo a me ka hoʻomanaʻo (Cypress De1ta 39K200 ma mua o 480 Kb o RAM);
- Ke kumu hoʻohālike manawa maʻalahi me nā kumu hoʻokele ala ʻē aʻe;
- Hiki ke hoʻololi i ka puka pin;
- Hiki ke hoʻokomo ʻia ma ka ʻōnaehana a hoʻonohonoho hou ʻia;
- Ka helu nui o nā ʻāpana I/O;
3. Nā ʻokoʻa a me nā pilina ma waena o FPGA a me CPLD
ʻO CPLD ka pōkole o ka polokalamu logic programmable paʻakikī, ʻo FPGA ka pōkole o ke kahua programmable gate array, ʻo ka hana o nā mea ʻelua he ʻano like ia, akā ʻokoʻa iki ke kumu hoʻokō, no laila hiki iā mākou ke haʻalele i ka ʻokoʻa ma waena o nā mea ʻelua, hui pū. i ʻōlelo ʻia ʻo ka polokalamu logic programmable a i ʻole CPLD/FPGA.Nui nā hui e hana ana i ka CPLD/FPGas, ʻo ka nui loa ʻekolu ʻo ALTERA, XILINX, a me LAT-TICE.He ikaika loa ka CPLD decomposition combinatorial logic function, hiki i ka macro unit ke decompose he kakini a oi aku paha ma mua o 20-30 combinatorial logic input.Eia nō naʻe, hiki i kahi LUT o FPGA ke mālama i ka loiloi hui pū ʻana o 4 mau hoʻokomo, no laila ua kūpono ʻo CPLD no ka hoʻolālā ʻana i nā loina hui pū ʻia e like me ka decoding.Eia naʻe, ʻo ke kaʻina hana o FPGA e hoʻoholo i ka nui o nā LUTs a me nā mea hoʻoiho i loko o ka chip FPGA he nui loa, pinepine mau tausani, hiki i ka CPLD ke hoʻokō wale i 512 logical units, a inā e māhele ʻia ke kumukūʻai chip e ka helu o ka loiloi. nā ʻāpana, ʻoi aku ka haʻahaʻa o ke kumukūʻai o ka FPGA ma mua o ka CPLD.No laila inā hoʻohana ʻia ka nui o nā mea hoʻoulu i ka hoʻolālā, e like me ka hoʻolālā ʻana i kahi loiloi manawa paʻakikī, a laila ʻo ka hoʻohana ʻana i kahi FPGA kahi koho maikaʻi.
ʻOiai ʻo FPGA a me CPLD nā polokalamu ASIC i hoʻolālā ʻia a he nui nā hiʻohiʻona maʻamau, ma muli o nā ʻokoʻa o ke ʻano o CPLD a me FPGA, loaʻa iā lākou nā ʻano ponoʻī:
- ʻOi aku ka maikaʻi o ka CPLD no ka hoʻopiha ʻana i nā algorithms like ʻole a me nā loiloi hui pū, a ʻoi aku ka maikaʻi o FPGA no ka hoʻopiha ʻana i ka loina sequential.I nā huaʻōlelo ʻē aʻe, ʻoi aku ka maikaʻi o ka FPGA no ka hoʻolālā waiwai flip-flop, ʻoiai ʻoi aku ka maikaʻi o CPLD no ka flip-flop limit a me ka huaʻōlelo waiwai waiwai.
- ʻO ka hoʻonohonoho hoʻomau ʻana o ka CPLD e hoʻoholo i ka lōʻihi o ka manawa a hiki ke ʻike ʻia, ʻoiai ke ʻano o ka hoʻokaʻawale ʻana o FPGA e hoʻoholo ai he hiki ʻole ke lohi.
- ʻOi aku ka maʻalahi o ka FPGA ma mua o CPLD i ka papahana.
- Hoʻolālā ʻia ʻo CPLD ma ka hoʻololi ʻana i ka hana logic o kahi kaapuni kūloko paʻa, ʻoiai ua hoʻolālā ʻia ʻo FPGA ma ka hoʻololi ʻana i ka uwea o ka pilina kūloko.
- Hiki ke hoʻolālā ʻia ʻo Fpgas ma lalo o nā puka logic, aʻo CPLDS ka papahana ma lalo o nā poloka logic.
- Hoʻohui ʻia ʻo FPGA ma mua o CPLD a ʻoi aku ka paʻakikī o ka hoʻolālā wili a me ka hoʻokō loiloi.
Ma keʻano laulā, ʻoi aku ka nui o ka mana o CPLD ma mua o ka FPGA, a ʻoi aku ka kiʻekiʻe o ka pae hoʻohui, ʻoi aku ka maopopo.
