Huahana Huahana

ʻO nā mea hoʻololi kūpono ke koho kūpono

ʻO ka hoʻohana ʻana i nā polokalamu Xilinx i nā polokalamu palekana o ka hanauna e hiki mai ana ʻaʻole wale e kamaʻilio i nā pilikia throughput a me ka latency, akā ʻo nā pono ʻē aʻe e pili ana i ka ʻae ʻana i nā ʻenehana hou e like me nā hiʻohiʻona aʻo mīkini, Secure Access Service Edge (SASE), a me ka post-quantum encryption.

Hāʻawi nā polokalamu Xilinx i ke kahua kūpono no ka wikiwiki ʻana o ka ʻenehana no kēia mau ʻenehana, no ka mea ʻaʻole hiki ke hoʻokō ʻia nā koi o ka hana me nā lako polokalamu wale nō.Ke hoʻomau nei ʻo Xilinx i ka hoʻomohala ʻana a me ka hoʻomaikaʻi ʻana i ka IP, nā mea hana, nā lako polokalamu, a me nā hoʻolālā kuhikuhi no nā ʻōnaehana palekana o kēia manawa a me ka hanauna hou.

Eia kekahi, hāʻawi nā polokalamu Xilinx i nā hale hoʻomanaʻo hoʻomanaʻo alakaʻi i ka ʻoihana me ka hoʻokaʻawale ʻana i ka IP hulina palupalu, e hana ana iā lākou i koho maikaʻi loa no ka palekana pūnaewele a me nā noi ahi.

Ke hoʻohana nei i nā FPGA ma ke ʻano he kaʻa kaʻa no ka palekana pūnaewele

Hoʻopili ʻia ke kaʻa i nā mea palekana (firewalls) ma nā pae he nui, a ua hana ʻia ka L2 encryption/decryption (MACSec) ma ka papa loulou (L2) nodes pūnaewele (nā hoʻololi a me nā mea ala).ʻO ka hana ma waho o ka L2 (MAC layer) ka mea maʻamau e komo i ka parsing hohonu, L3 tunnel decryption (IPSec), a me ka hoʻopunipuni SSL me ka TCP/UDP traffic.ʻO ka hoʻoili ʻana i ka packet e pili ana i ka parsing a me ka hoʻokaʻawale ʻana i nā ʻeke e komo mai ana a me ka hoʻoili ʻana i nā puke kaʻa nui (1-20M) me ka throughput kiʻekiʻe (25-400Gb/s).

Ma muli o ka nui o nā kumuwaiwai computing (cores) i koi ʻia, hiki ke hoʻohana ʻia nā NPU no ka hoʻoili ʻana i ka packet wikiwiki kiʻekiʻe, akā ʻaʻole hiki i ka latency haʻahaʻa, kiʻekiʻe ka hana scalable kaʻa kaʻa no ka mea ua hana ʻia ke kaʻa me ka hoʻohana ʻana i nā cores MIPS/RISC a me ka hoʻonohonoho ʻana i kēlā mau cores. ma muli o ko lākou loaʻa paʻakikī.Hiki i ka hoʻohana ʻana i nā mea hana palekana e pili ana i ka FPGA ke hoʻopau pono i kēia mau palena o ka CPU a me ka NPU-based architecture.

ʻO ka hana palekana pae noiʻi ma nā FPGA

He kūpono nā FPGA no ka hoʻoponopono ʻana i ka palekana inline i nā pā ahi e hiki mai ana no ka mea ua kūleʻa lākou i ka pono no ka hana kiʻekiʻe, hiki ke maʻalahi, a me ka hana haʻahaʻa haʻahaʻa.Eia hou, hiki i nā FPGA ke hoʻokō i nā hana palekana o ka pae noiʻi, hiki ke mālama hou i nā kumuwaiwai computing a hoʻomaikaʻi i ka hana.

ʻO nā hiʻohiʻona maʻamau o ka hana palekana noi ma FPGA

- TTCP offload engine

- Hoʻohālikelike ʻōlelo maʻamau

- Ka hana hoʻopunipuni Asymmetric (PKI).

- TLS hana