Xilinx/XC7K480T-2FFG1156I/XC7K480T/IC BOM FPGA/kaapuni hoʻohui

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XC7K480T-2FFG1156I FPGAs Nānā
Ka wehewehe nui
Xilinx® 7 series FPGAs he ʻehā ʻohana FPGA e kamaʻilio ana i ka piha piha o nā pono ʻōnaehana, mai ke kumu kūʻai haʻahaʻa, ʻano kumu liʻiliʻi, nā kumu kūʻai, nā noi kiʻekiʻe a hiki i ka bandwidth hoʻohui kiʻekiʻe kiʻekiʻe, ka mana logic, a me ka hiki ke hana hōʻailona. no nā noi hana kiʻekiʻe loa.Aia nā FPGA 7 series:
• ʻOhana Spartan®-7: Hoʻonui ʻia no ke kumu kūʻai haʻahaʻa, ka mana haʻahaʻa, a me ka hana I/O kiʻekiʻe.Loaʻa i ke kumu kūʻai haʻahaʻa, liʻiliʻi liʻiliʻi loa no ka PCB kapuaʻi liʻiliʻi.
• ʻOhana Artix®-7: Hoʻonui ʻia no nā noi haʻahaʻa haʻahaʻa e koi ana i nā transceivers serial a me DSP kiʻekiʻe a me ka logic throughput.Hāʻawi i ka helu haʻahaʻa haʻahaʻa o nā kumu kūʻai no nā noi kiʻekiʻe, nā kumu kūʻai.
• Kintex®-7 Family: Hoʻonui ʻia no ka hana kumu kūʻai maikaʻi loa me ka hoʻomaikaʻi ʻana o 2X i hoʻohālikelike ʻia me ka hanauna mua, e hiki ai i kahi papa hou o FPGA.
• ʻOhana Virtex®-7: Hoʻonui ʻia no ka hoʻokō ʻana o ka ʻōnaehana kiʻekiʻe a me ka hiki ke hoʻomaikaʻi 2X i ka hana ʻōnaehana.ʻO nā mea hana kiʻekiʻe loa i hoʻohana ʻia e ka ʻenehana hoʻohui silicon interconnect (SSI).
Kūkulu ʻia ma luna o kahi ʻenehana kaʻina hana kiʻekiʻe, hana kiʻekiʻe, haʻahaʻa haʻahaʻa (HPL), 28 nm, high-k metal gate (HKMG), 7 series FPGAs e hiki ai i ka hoʻonui ʻole ʻia o ka hana ʻōnaehana me 2.9 Tb/ s o I/O bandwidth, 2 miliona logic cell capacity, a me 5.3 TMAC/s DSP, oiai e hoopau ana i ka mana he 50% emi iho ma mua o na mea hana o ka hanauna mua e haawi i kahi koho koho piha i ka ASSPs a me ASICs.
Nā hiʻohiʻona
• ʻO ka loiloi FPGA kūlana kiʻekiʻe e pili ana i ka ʻenehana 6-input lookup table (LUT) hiki ke hoʻonohonoho ʻia e like me ka hoʻomanaʻo puʻupuʻu.
• 36 Kb pālua-puka poloka RAM me ka manaʻo FIFO i kūkulu ʻia no ka hoʻopaʻa ʻana i ka ʻikepili ma ka chip.
• ʻenehana SelectIO™ hana kiʻekiʻe me ke kākoʻo ʻana i nā pilina DDR3 a hiki i ka 1,866 Mb/s.
• Kiʻekiʻe-wikiwiki hoʻohui serial me ka i kūkulu-i loko o multi-gigabit transceivers mai 600 Mb / s i ka palena kiʻekiʻe o 6.6 Gb / s a ​​hiki i 28.05 Gb / s, e hāʻawi ana i kahi kūikawā haʻahaʻa-mana, optimized no chip-to-chip interfaces. .
• He mea hoʻohana configurable analog interface (XADC), e hoʻokomo ana i ʻelua 12-bit 1MSPS analog-to-digital converters me nā mea ʻike wela a me nā lako lako.
• Nā ʻāpana DSP me 25 x 18 multiplier, 48-bit accumulator, a me pre-adder no ka kānana hana kiʻekiʻe, me ke kānana coefficient symmetric optimized.
• Nā kīleʻa hoʻokele uaki ikaika (CMT), e hui pū ana i ka loop loop-locked loop (PLL) a me ka hui ʻana o ke ʻano hoʻokele clock manager (MMCM) no ka pololei kiʻekiʻe a me ka jitter haʻahaʻa.
• Poloka hoʻohui ʻia no PCI Express® (PCIe), no ka hoʻolālā ʻana i ka x8 Gen3 Endpoint a me Root Port.
• Nui nā ʻano koho hoʻonohonoho, me ke kākoʻo ʻana i nā mea hoʻomanaʻo waiwai, 256-bit AES encryption me HMAC/SHA-256 hōʻoia, a me ka ʻike a me ka hoʻoponopono SEU i kūkulu ʻia.
• ʻO ke kumu kūʻai haʻahaʻa, ka uea-paʻa, lidless flip-chip, a me ka hōʻailona kiʻekiʻe integrity flipchip packaging e hāʻawi ana i ka neʻe maʻalahi ma waena o nā lālā o ka ʻohana i loko o ka pūʻolo like.Loaʻa nā pūʻolo āpau ma Pb-noa a me nā pūʻolo i koho ʻia ma ke koho Pb.
• Hoʻolālā ʻia no ka hana kiʻekiʻe a me ka mana haʻahaʻa me 28 nm, HKMG, kaʻina HPL, 1.0V ʻenehana kaʻina hana uila a me ka koho 0.9V kumu uila no ka mana haʻahaʻa.
ʻO ka Xilinx FPGAs (Field Programmable Gate Array) moʻo XC7K480T-2FFG1156I ʻo FPGA, Kintex-7, MMCM, PLL, 400 I/O's, 710 MHz, 477760 Pūnaewele, 970 mV a i 1.01 V, ʻAi ʻAi ʻAi a me FCBGA. me ka ʻikepili, ka waiwai, ke kumu kūʻai mai Authorized Distributors ma FPGAkey.com, a hiki iā ʻoe ke ʻimi no nā huahana FPGAs ʻē aʻe.
Nā hiʻohiʻona
ʻO ka loina FPGA kūlana kiʻekiʻe e pili ana i ka ʻenehana 6-input lookup table (LUT) i hiki ke hoʻonohonoho ʻia e like me ka hoʻomanaʻo ʻana.
36 Kb pahu lua-puka RAM me ka manaʻo FIFO i kūkulu ʻia no ka hoʻopaʻa ʻana i ka ʻikepili ma luna o ka chip.
ʻenehana SelectIO hana kiʻekiʻe me ke kākoʻo no nā pilina DDR3 a hiki i 1,866 Mb/s.
Kiʻekiʻe-wikiwiki hui pū me nā transceivers multi-gigabit i kūkulu ʻia mai 600 Mb / s a ​​hiki i nā helu kiʻekiʻe o 6.6 Gb / s a ​​hiki i 28.05 Gb / s, e hāʻawi ana i kahi mode haʻahaʻa haʻahaʻa kūikawā, i hoʻopaʻa ʻia no nā interface chip-to-chip.
He mea hoʻohana e hoʻololi ana i ka analog (XADC), e hoʻokomo ana i ʻelua mau mea hoʻololi analog-to-digital 12-bit 1MSPS me nā mea ʻike wela a me nā lako lako.
ʻO nā ʻāpana DSP me 25 x 18 multiplier, 48-bit accumulator, a me pre-adder no ka kānana hana kiʻekiʻe, me ke kānana coefficient symmetric optimized.
ʻO nā tile hoʻokele uaki ikaika (CMT), ka hui pū ʻana i ka loop-locked loop (PLL) a me ka hui ʻana o ke ʻano hui ʻana (MMCM) poloka no ka pololei kiʻekiʻe a me ka jitter haʻahaʻa.
Paʻa i hoʻohui ʻia no PCI Express (PCIe), no ka hoʻolālā ʻana i ka x8 Gen3 Endpoint a me Root Port.
Nui nā ʻano koho hoʻonohonoho, me ke kākoʻo no nā mea hoʻomanaʻo waiwai, 256-bit AES encryption me HMAC/SHA-256 authentication, a me ka ʻike a me ka hoʻoponopono SEU i kūkulu ʻia.
ʻO ke kumu kūʻai haʻahaʻa, uea-boa, lidless flip-chip, a me ka hōʻailona kiʻekiʻe integrity flipchip packaging e hāʻawi ana i ka neʻe maʻalahi ma waena o nā lālā o ka ʻohana i ka pūʻolo like.Loaʻa nā pūʻolo āpau ma Pb-noa a me nā pūʻolo i koho ʻia ma ke koho Pb.
Hoʻolālā ʻia no ka hana kiʻekiʻe a me ka mana haʻahaʻa loa me 28 nm, HKMG, kaʻina HPL, 1.0V ʻenehana kaʻina hana uila a me ka koho 0.9V koʻikoʻi no ka mana haʻahaʻa.