Kaapuni hoʻohui hou a me nā mea uila 5M240ZT100C5N ic mea kūʻai i kahi wahi kūʻai i ka lawelawe BOM
Huahana Huahana
ANO | HOIKE |
Māhele | Nā Kaapuni Hoʻohui (IC) |
ʻO Mfr | Intel |
moʻo | MAX® V |
Pūʻolo | pā |
Pūʻolo maʻamau | 90 |
Kūlana Huahana | ʻeleu |
ʻAno polokalamu | Ma System Programmable |
Manawa hoʻopaneʻe tpd(1) Max | 7.5 ns |
Hoʻolako Voltage – Loko | 1.71V ~ 1.89V |
Ka helu o nā ʻElemu Logic/Blocks | 240 |
Ka helu o nā Macrocells | 192 |
Ka helu o I/O | 79 |
Ka Mahana Hana | 0°C ~ 85°C (TJ) |
ʻAno kau ʻana | Mauna ʻili |
Pūʻolo / hihia | 100-TQFP |
Pūʻolo Mea Mea Hoʻolako | 100-TQFP (14×14) |
Helu Huahana Kumu | 5M240Z |
A. He aha nā ʻāpana FPGA maʻamau
I kēia manawa, hele mai nā pahu FPGA ma ka mākeke mai Xilinx a me Altera, kahi e noho ai ma mua o 80% o ka māhele mākeke FPGA.ʻO nā huahana mea hana FPGA ʻē aʻe no kekahi mau noi kikoʻī, no ka laʻana, hana nui ʻo Actel i ka anti-fuse structure FPGAs e hoʻokō i nā kūlana noi noi nui loa o nā huahana aerospace.Eia nā huahana ʻelele o nā hui ʻelua, ʻo Altera a me Xilinx.
Nā huahana maʻamau a Altera
Ua māhele ʻia nā mea FPGA o Altera i ʻekolu pūʻulu: ʻo kekahi ka moʻo Cyclone haʻahaʻa;ʻO ka lua ka moʻo Stratix kiʻekiʻe, a ʻo ke kolu ʻo ka Arriva series i hiki ke maʻalahi i ka ASICized ma waena o nā mea ʻelua.
1. no nā FPGA Stratix moʻo kiʻekiʻe
Hiki i nā Stratix series FPGAs ke kōkua i nā mea hoʻohana e hoʻohaʻahaʻa i ka pōʻino a me ka hana kiʻekiʻe i ka hiki ke hoʻomaka i nā huahana kiʻekiʻe loa.ʻO ka hui pū ʻana i nā hiʻohiʻona kiʻekiʻe, hana kiʻekiʻe, a me nā hiʻohiʻona waiwai, hiki i ka ʻohana Stratix o FPGA ke hoʻohui i nā hiʻohiʻona hou aʻe a hoʻonui i ka bandwidth ʻōnaehana.ʻO nā hiʻohiʻona o ka ʻohana Stratix o nā hanauna huahana he kipi a hoʻomau i ka ulu ʻana.Hōʻike ʻia nā lā hoʻomaka a me nā ʻenehana kaʻina hana o ka ʻohana Stratix o FPGA ma ka Papa 1-1.
Papa 1-1 Stratix Series Papa
ʻO nā hiʻohiʻona Stratix FPGA a me Stratix GX nā hiʻohiʻona mua loa ma ka ʻohana Stratix FPGA o Altera.Hoʻokomo kēia ʻohana o nā FPGA hana kiʻekiʻe i ka DSP hardcore intellectual property (IP) modules a me ka hoʻomanaʻo ʻana o TriMatrix on-chip a Altera i hoʻohana nui ʻia a me ka hoʻolālā I/O maʻalahi.
Hoʻokomo nā hiʻohiʻona Stratix II FPGA a me Stratix II GX i ka hoʻolālā Adaptive Logic Module (ALM), kahi e pani ai i ka LUT 4-input me kahi papa kiʻekiʻe 8-input segmented lookup table (LUT).II GX FPGA a ua paipai nui ʻia lākou no nā hoʻolālā hou.
ʻO nā Stratix III FPGA ka mana haʻahaʻa haʻahaʻa o ka ʻoihana, hana kiʻekiʻe 65nm FPGAs.Hiki iā ia ke hoʻohana i ke ʻano loiloi (L), ka hoʻomanaʻo, a me ka hoʻonui DSP (E) e hoʻohui i nā koi kumu waiwai hoʻolālā o ka mea hoʻohana me ka ʻole o ka hoʻolālā ʻana me nā kumuwaiwai ʻoi aku ka nui ma mua o ka mea e pono ai, no laila e mālama ai i nā papa, hoʻopōkole i ka manawa hoʻohui, a hoʻemi i nā kumukūʻai.hoʻolālā nui ʻia nā FPGA hoʻolālā III no ka hoʻoponopono ʻōnaehana kumu kiʻekiʻe no nā noi he nui.
Hāʻawi nā Stratix IV FPGA i ka mea kiʻekiʻe loa, ka hana maikaʻi loa, a me ka hoʻohana mana haʻahaʻa loa o kekahi 40nm FPGA.Hāʻawi ka ʻohana Stratix IV FPGA i nā mea i hoʻonui ʻia (E) a i hoʻonui ʻia me nā transceivers (GX a me GT) e hoʻokō i nā pono o nā mākeke he nui a me nā noi e like me ke kelepona uila a me ka laina paʻa, pūʻali koa, hoʻolaha, a me nā mea hou aku, kēia 40nm FPGA kiʻekiʻe. Aia ka ʻohana i nā transceiver 11.3 Gbps maikaʻi loa ma ka papa.
Loaʻa nā Stratix V FPGA i ka bandwidth kiʻekiʻe loa a me ka hoʻohui pūnaewele kiʻekiʻe loa o kekahi 28nm FPGA a maʻalahi loa.Loaʻa i ka ʻohana hāmeʻa nā hiʻohiʻona 14.1 Gbps (GS a me GX) me ka backplane kūpono, chip-to-chip, a me chip-to-module functionality, a me 28G (GT) transceiver models e kākoʻo ana i ka chip-to-chip a me ka chip-to- modula me ka ʻoi aku o hoʻokahi miliona LEs a me 4,096 mau modula DSP kūpono-tunable.
ʻO Altera Stratix 10 FPGA me ka ʻenehana 14nm triple-gate o Intel e hāʻawi i ka hana maikaʻi loa, ka bandwidth, a me ka hoʻohui pūnaewele o kekahi FPGA, a haʻahaʻa loa ka hoʻohana mana.ʻO nā mea hoʻolālā 10 e hōʻike ana i nā transceivers 56Gbps, 28Gbps backplanes, floating-point digital signal processing (DSP) hana, a me ke kākoʻo no ka IEEE 754 i hoʻonui ʻia ʻO ka Stratix 10 SoC ka ʻohana SoC kiʻekiʻe kiʻekiʻe loa ma ka ʻenehana transistor triple-gate a Intel me kahi mea hou aʻe. -generation hard-core processor system optimized for the best performance per watt.