LCMXO2-2000HC-4TG100I FPGA CPLD MachXO2-2000HC 2.5V/3.3V
Huahana Huahana
| Pbfree Code | ʻAe |
| Rohs Code | ʻAe |
| Māhele Life Cycle Code | ʻeleu |
| Mea Hana Ihs | LATTICE SEMICONDUCTOR CORP |
| Māhele Pūʻolo Code | QFP |
| Hōʻike pūʻolo | QFP, QFP100,.63SQ,20 |
| Helu Pin | 100 |
| E kiʻi i ka Code Compliance | hoʻokō |
| ECCN Code | EAR99 |
| HTS Code | 8542.39.00.01 |
| Mea Hana Hana Samacsys | Lattice Semiconductor |
| Hiʻona hou | E HANA HOI MA 3.3 V NOMINAL SUPPLY |
| Ka pinepine Uki-Max | 133 MHz |
| JESD-30 Code | S-PQFP-G100 |
| JESD-609 Code | e3 |
| Ka lōʻihi | 14 mm |
| Ka Papa Hoʻomaʻamaʻa | 3 |
| Ka helu o nā mea hoʻokomo | 79 |
| Ka helu o nā Pūnaehana Loko | 2112 |
| Ka helu o nā mea hoʻopuka | 79 |
| Ka helu o nā Terminals | 100 |
| Hana wela-Max | 100 °C |
| Hana wela-Min | -40 °C |
| Mea Kino Puke | PLASTIK/EPOXY |
| Kāhea pūʻolo | QFP |
| Pūʻolo helu kaulike | QFP100,.63SQ,20 |
| Hui Pūʻolo | KAHIKI |
| Kāhua pūʻolo | PALAPALA |
| Keʻano hoʻopaʻa | PAʻI |
| ʻO ka wela o ke kahe hou ʻana (Cel) | 260 |
| Nā lako mana | 2.5/3.3 V |
| ʻAno Logic Programmable | KĀHĀNĀ PALAPALA PALAPALA |
| Kūlana kūpono | ʻAʻole kūpono |
| Noho Kiʻekiʻe-Max | 1.6 mm |
| Voltage-Max | 3.465 V |
| Voltage-Min | 2.375 V |
| Voltage-Nom | 2.5 V |
| Mauna ʻili | ʻAE |
| Hoʻopau ʻia | ʻO ke kinona (Sn) |
| Puka Pahu | Eheu GULL |
| Kūlana Kūlana | 0.5 mm |
| Kūlana Kūlana | QUAD |
| Manawa@Peak Reflow Mahana-Max (s) | 30 |
| Laulā | 14 mm |
Hoʻolauna Huahana
FPGAʻO ia ka huahana o ka hoʻomohala hou ʻana ma ke kumu o nā polokalamu hiki ke hoʻonohonoho ʻia e like me PAL a me GAL, a he chip hiki ke hoʻolālā ʻia e hoʻololi i ka hoʻolālā o loko.ʻO FPGA kahi ʻano kaapuni semi-custom ma ke kahua o ka application-specific integrated circuit (ASIC), ʻaʻole ia e hoʻoponopono wale i nā hemahema o ke kaapuni maʻamau, akā lanakila pū nō hoʻi i nā hemahema o ka helu palena o nā kaapuni puka o ka polokalamu programmable kumu.Mai ka hiʻohiʻona o nā polokalamu chip, ʻo ka FPGA ponoʻī ka mea i hoʻohui ʻia i loko o kahi kaapuni semi-customized, aia kahi module hoʻokele kikohoʻe, kahi ʻāpana i kūkulu ʻia, kahi ʻāpana hoʻopuka a me kahi ʻāpana komo.
Nā ʻokoʻa ma waena o FPGA, CPU, GPU, a me ASIC
(1) Wehewehe: ʻO ka FPGA kahi kahua i hoʻonohonoho ʻia i ka logic gate array;ʻO ka CPU ke kikowaena hana kikowaena;ʻO ka GPU he mea hana kiʻi kiʻi;ʻO Asics nā mea hana kūikawā.
(2) Ka mana helu a me ka ikaika o ka ikehu: I ka mana hoʻopili FPGA, ʻoi aku ka maikaʻi o ka lākiō ikehu;Loaʻa i ka CPU ka mana helu haʻahaʻa a maikaʻi ʻole ka lakene o ka ikehu;Ka mana helu GPU kiʻekiʻe, ka lākiō ikehu;ASIC mana helu helu kiʻekiʻe, ikehu lākiō.
(3) Mākēneki wikiwiki: FPGA mākēkē wikiwiki;ʻO ka wikiwiki o ka mākeke CPU, ke oʻo o ka huahana;He wikiwiki ka wikiwiki o ka mākeke GPU, ua oʻo ka huahana;Ua lohi ʻo Asics i ka mākeke a loaʻa kahi pōʻai hoʻomohala lōʻihi.
(4) Uku: He haʻahaʻa ko FPGA hoʻāʻo a me ka hewa;Ke hoʻohana ʻia ka GPU no ka hoʻoili ʻikepili, ʻoi aku ka kiʻekiʻe o ke kumukūʻai ʻāpana;Ke hoʻohana ʻia ka GPU no ka hoʻoili ʻikepili, kiʻekiʻe ke kumu kūʻai.He kumukūʻai kiʻekiʻe ka ASIC, hiki ke hana hou ʻia, a hiki ke hoʻemi maikaʻi ʻia ke kumukūʻai ma hope o ka hana nui.
(5) Hana: He ikaika ka hiki ke hoʻoili ʻikepili FPGA, hoʻolaʻa maʻamau;ʻO ka GPU maʻamau (nā ʻōlelo aʻoaʻo + hana);Loaʻa i ka hoʻoili ʻikepili GPU ka versatility ikaika;Loaʻa iā ASIC ka mana helu AI ikaika loa a ʻo ia ka mea hoʻolaʻa loa.
Nā hiʻohiʻona noi FPGA
(1)kahua kamaʻilio: Pono ke kahua kamaʻilio i nā ʻano kaʻina hana protocol kamaʻilio kiʻekiʻe, ma ka ʻaoʻao ʻē aʻe, ua hoʻololi ʻia ka protocol kamaʻilio i kēlā me kēia manawa, ʻaʻole kūpono no ka hana ʻana i kahi chip kūikawā, no laila ua lilo ka FPGA hiki ke hoʻololi i ka hana i ka koho mua.
Ua hoʻohana nui ka ʻoihana kelepona iā FPGas.Ke hoʻololi mau nei nā kūlana kelepona a he paʻakikī loa ke kūkulu ʻana i nā lako kelepona, no laila, ʻo ka hui e hāʻawi ana i nā ʻōnaehana kelepona e hopu mua i ka māhele mākeke nui loa.He manawa lōʻihi ka hana ʻana o Asics, no laila hāʻawi ʻo FPGas i kahi manawa pōkole.Ua hoʻomaka nā mana mua o nā lako kelepona e hoʻohana i ka FPgas, kahi i alakaʻi ai i nā hakakā kumukūʻai FPGA.ʻOiai ʻaʻole pili ke kumukūʻai o FPGas i ka mākeke simulation ASIC, ʻo ke kumukūʻai o nā chips telecom.
(2)Māhele algorithm: Loaʻa i ka FPGA ka mana hana ikaika no nā hōʻailona paʻakikī a hiki ke hana i nā hōʻailona multidimensional.
(3) Embedded field: Ke hoʻohana nei i ka FPGA e kūkulu i kahi kaiapuni i hoʻopili ʻia, a laila kākau i kekahi polokalamu i hoʻopili ʻia ma luna o ia mea, ʻoi aku ka paʻakikī o ka hana transactional, a ʻoi aku ka liʻiliʻi o ka hana o FPGA.
(4)Palekanakahua kiaʻi: I kēia manawa, paʻakikī ka CPU i ka hana ʻana i nā kaila he nui a hiki ke ʻike a hoʻopaʻa ʻia, akā hiki ke maʻalahi me ka FPGA, ʻoi aku hoʻi ma ke kahua o nā algorithms kiʻi.
(5) Ke kahua ʻenehana ʻenehana: Hiki i ka FPGA ke hoʻokō i ka mana kaʻa kaʻa he nui, ʻo ka mana o ka mana kaʻa i kēia manawa no ka hapa nui o ka hoʻohana ʻana i ka ikehu honua, ma lalo o ke ʻano o ka mālama ʻana i ka ikehu a me ka pale ʻana i ke kaiapuni, hiki i ka wā e hiki mai ana o kēlā me kēia ʻano o nā kaʻa kaʻa pololei. hiki ke hoʻohana ʻia, hiki i kahi FPGA ke hoʻomalu i ka nui o nā kaʻa.
