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huahana

Kipa IC kumu i hoʻolālā ʻia XCVU440-2FLGA2892I IC FPGA 1456 I/O 2892FCBGA

wehewehe pōkole:


Huahana Huahana

Huahana Huahana

Huahana Huahana

ANO HOIKE
Māhele Nā Kaapuni Hoʻohui (IC)

Hoʻokomo ʻia

Nā FPGA (Field Programmable Gate Array)

ʻO Mfr AMD Xilinx
moʻo Virtex® UltraScale™

 

Pahu
Kūlanad Pūʻolo 1
Kūlana Huahana ʻeleu
Ka helu o nā LAB/CLB 316620
Ka helu o nā Elements Logic / Cells 5540850
Huina RAM Bits 90726400
Ka helu o I/O 1456
Voltage - Hoʻolako 0.922V ~ 0.979V
ʻAno kau ʻana Mauna ʻili
Ka Mahana Hana -40°C ~ 100°C (TJ)
Pūʻolo / hihia 2892-BBGA, FCBGA
Pūʻolo Mea Mea Hoʻolako 2892-FCBGA (55×55)
Helu Huahana Kumu XCVU440

Ke hoʻohana nei i nā FPGA ma ke ʻano he kaʻa kaʻa no ka palekana pūnaewele

Hoʻopili ʻia ke kaʻa i nā mea palekana (firewalls) ma nā pae he nui, a ua hana ʻia ka L2 encryption/decryption (MACSec) ma ka papa loulou (L2) nodes pūnaewele (nā hoʻololi a me nā mea ala).ʻO ka hana ma waho o ka L2 (MAC layer) ka mea maʻamau e komo i ka parsing hohonu, L3 tunnel decryption (IPSec), a me ka hoʻopunipuni SSL me ka TCP/UDP traffic.ʻO ka hoʻoili ʻana i ka packet e pili ana i ka parsing a me ka hoʻokaʻawale ʻana i nā ʻeke e komo mai ana a me ka hoʻoili ʻana i nā puke kaʻa nui (1-20M) me ka throughput kiʻekiʻe (25-400Gb/s).

Ma muli o ka nui o nā kumuwaiwai computing (cores) i koi ʻia, hiki ke hoʻohana ʻia nā NPU no ka hoʻoili ʻana i ka packet wikiwiki kiʻekiʻe, akā ʻaʻole hiki i ka latency haʻahaʻa, kiʻekiʻe ka hana scalable kaʻa kaʻa no ka mea ua hana ʻia ke kaʻa me ka hoʻohana ʻana i nā cores MIPS/RISC a me ka hoʻonohonoho ʻana i kēlā mau cores. ma muli o ko lākou loaʻa paʻakikī.Hiki i ka hoʻohana ʻana i nā mea hana palekana e pili ana i ka FPGA ke hoʻopau pono i kēia mau palena o ka CPU a me ka NPU-based architecture.

ʻO ka hana palekana pae noiʻi ma nā FPGA

He kūpono nā FPGA no ka hoʻoponopono ʻana i ka palekana inline i nā pā ahi e hiki mai ana no ka mea ua kūleʻa lākou i ka pono no ka hana kiʻekiʻe, hiki ke maʻalahi, a me ka hana haʻahaʻa haʻahaʻa.Eia hou, hiki i nā FPGA ke hoʻokō i nā hana palekana o ka pae noiʻi, hiki ke mālama hou i nā kumuwaiwai computing a hoʻomaikaʻi i ka hana.

ʻO nā hiʻohiʻona maʻamau o ka hana palekana noi ma FPGA

- TTCP offload engine

- Hoʻohālikelike ʻōlelo maʻamau

- Ka hana hoʻopunipuni Asymmetric (PKI).

- TLS hana

Nā ʻenehana palekana o ka hanauna hou e hoʻohana ana i nā FPGA

Nui nā asymmetric algorithms i hiki ke hoʻololi ʻia e nā kamepiula quantum.ʻO nā algorithm palekana Asymmetric e like me RSA-2K, RSA-4K, ECC-256, DH, a me ECCDH ka mea i hoʻopilikia nui ʻia e nā ʻenehana helu quantum.Ke ʻimi ʻia nei nā hoʻokō hou o nā algorithm asymmetric a me NIST standardization.

ʻO nā manaʻo o kēia manawa no ka hoʻopili ʻana ma hope o ka quantum e loaʻa ke ala Ring-on-Error Learning (R-LWE) no

- Kākoʻo Kiʻi Kūlohelohe (PKC)

- Nā pūlima kikohoʻe

- Hana kī

ʻO ka hoʻokō ʻana i ka cryptography kī lehulehu e pili ana i kekahi mau hana makemakika kaulana (TRNG, Gaussian noise sampler, polynomial add, binary polynomial quantifier division, multiplication, etc.).Loaʻa ka IP FPGA IP no ka nui o kēia mau algorithm a hiki ke hoʻokō pono ʻia me ka hoʻohana ʻana i nā poloka hale FPGA, e like me DSP a me AI engines (AIE) i nā polokalamu Xilinx i kēia manawa a me ka hanauna hou.

Hōʻike kēia pepa keʻokeʻo i ka hoʻokō ʻana i ka palekana L2-L7 me ka hoʻohana ʻana i kahi papahana programmable i hiki ke hoʻolālā ʻia no ka wikiwiki o ka palekana ma nā ʻaoʻao ʻaoʻao / komo a me nā pā ahi (NGFW) i nā ʻoihana ʻoihana.


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